ASIC Physical Design
1,641 open positions
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Senior ASIC RTL Design Engineer, AI Hardware CerebrasRemote $200k–$200k5d Design and develop next-generation Cerebras Wafer Scale Engine (WSE) AI chips, focusing on high-performance, power-efficient, and scalable RTL solutions.
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2027 Intern - SoC Digital Engineer MotorolasolutionsPlantation, FL, US 5d Develop the digital portion of mixed signal ICs for hi-reliability public safety communications systems using CMOS technologies.
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Staff Engineer, ASIC STA MicronBengaluru, India 5d Staff Engineer leading Static Timing Analysis (STA), Synthesis, and Logic Equivalence Checking (LEC) for complex mixed-signal ASIC designs in memory and storage solutions.
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Senior FPGA & Digital Hardware Engineer↗ GE HealthCareWaukesha, WI, US 5d Design and verify digital circuit boards and FPGA-based subsystems for high-performance MRI data acquisition, control, processing, and communications.
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ASIC Engineer I, Annapurna Labs, Early Career - 2027↗ Amazon Web ServicesAustin, TX, US $116k–$116k5d Design and implement RTL for digital logic blocks and develop verification environments for custom silicon products like Graviton, Trainium, and Inferentia.
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Physical Design Engineer AlteraSan Jose, California, United States $105k–$105k5d Physical implementation of next-generation FPGA products, optimizing designs for timing, power, area, and manufacturability.
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Senior FPGA & Digital Hardware Engineer GehcWaukesha, US 5d Design and verify digital circuit boards and FPGA-based subsystems for high-performance data acquisition, control, processing, and communications in next-generation MRI platforms.
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Hardware Engineer - Board Design | 5 - 8 yrs CiscoBangalore, India 5d Designing high-quality, power-efficient hardware systems for Service Provider routers using advanced SERDES technology.
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Digital IC Design Engineering Intern SemtechCAN - Ottawa, ON, CA $54k–$54k5d Design, development, verification, and implementation of digital circuits for high-performance optical networking and data communications products.
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Physical design CAD engineer MarvellYokneam, IL 5d Physical design and methodology for next-generation high-performance processor chips in leading-edge CMOS processes for server, 5G/6G, automotive, and networking applications.
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VLSI Engineer II - 0T1192 HpeSunnyvale, California, United States of America $106k–$214k5d Designs, simulates, tests, and implements VLSI components, circuits, and hardware systems for computer, server, and networking architectures.
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Physical Design Engineer, ML4PD TenstorrentAustin $100k–$100k6d Physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout.
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Principal Digital Design Engineer Renesas-ElectronicsSan Jose, CALIFORNIA, us $190k–$190k6d Architect, design, and implement digital and mixed-signal integrated circuits (ICs) for automotive, industrial, and IoT applications, leading development from conception to production release.
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Expert FPGA / ASIC Numérique - Architecture ou Vérification - Industrie - Toulouse Sopra-SteriaToulouse, Occitanie, fr 6d Expert in FPGA/ASIC digital architecture or verification for critical embedded and industrial systems with real-time and safety constraints.
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ASIC Chip Lead BroadcomUSA-CA San Jose Innovation Drive $144k–$144k6d Lead end-to-end development of System-on-Chip (SoC) solutions from RTL design through mass production.
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Custom Library Design Lead AppleSan Diego, United States of America 6d Lead custom digital circuits team and library development for state-of-the-art ASIC processor design, delivering high-performance, low-power standard cells and power management cells to millions of customers.
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Lead Application Engineer CadenceSHANGHAI, CN 6d Provide technical support for digital IC design implementation, product demonstrations, and sales presentations.
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Senior System and Manufacturing CoDesign Architect - Power, Thermal and Packaging NVIDIAUS, CA, Santa Clara $196k–$196k6d Define physical limits of chip performance and develop cross-domain solutions to overcome power, thermal, and packaging constraints in high-performance computing systems.
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Qubit Control Physical Design Engineer IntelUS, Oregon, Hillsboro $142k–$142k6d Deliver high-performance physical designs for advanced semiconductor technologies, optimizing power, performance, and area (PPA) from synthesis to sign-off.
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Digital IC Design Engineer - USB Products Texas InstrumentsDallas, TX, United States 6d Design next-generation USB 2.0 and eUSB2 hubs, hosts, and bridges for Enterprise AI and IoT applications.
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Hardware / Performance Architect↗ Epic Blockchain TechnologiesNorth York, ON, CA $120k–$120k6d Define micro-architecture and performance modeling for a large, regular compute-array inference ASIC, translating system-level intent into block specifications for RTL and compiler teams.
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Physical Design Engineer- Singapore↗ Picoheart (sg) Pte. Ltd.Outram, S00, SG 6d Own physical implementation of critical blocks/subsystems/SOCs from netlist to GDS, driving PPA optimization and signoff closure.
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Digital Design Engineer AnalogdevicesIndia, Hyderabad 6d Design and develop digital integrated circuits, executing the complete design flow from specification to implementation for industry-standard interfaces.
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Senior Physical Design Engineer↗
GoogleMountain View, CA, US
$163k–$163k6d
Develop full-chip ASIC RTL-to-GDS physical implementation to optimize Power, Performance, and Area (PPA) for Google's direct-to-consumer products.
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Senior Digital Design Engineer - MCU NXP SemiconductorsCatania, Provincia di Catania $51k–$51k6d Lead full digital IC design flow for complex System-on-Chip (SOC) to create high-performance micro-controllers for industrial automation and autonomous home applications.
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Staff SoC Architect GraphcoreBristol 7d Define SoC architecture for next-generation AI acceleration platforms, specifying subsystems, interfaces, and interconnects to guide implementation and validation.
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Physical Design Intern AmbiqmicroincSingapore 7d Intern role supporting block-level physical implementation for ultra-low power System-on-Chip (SoC) designs in advanced process nodes.
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Silicon Digital IP / Subsystem Architect AsteralabsBengaluru 7d Define architecture and technical direction for complex semiconductor IPs and subsystems, owning the definition from requirements through implementation.
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Digital/FPGA Engineer↗ Per Vices CorporationToronto, ON, CA 7d Design, simulate, implement, and validate FPGA-based architectures for Software Defined Radios (SDRs) interfacing high-speed data buses with converters.
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Staff / Senior Staff Physical Design Engineer (IC Backend)↗ Leadtop TechnologyClementi, S00, SG 7d Lead physical design tasks from netlist to GDSII, including floorplanning, P&R, verification, and tapeout for advanced process nodes.
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ASIC Digital Design, Staff Engineer↗ SynopsysPorto, P13, PT 7d Design and implement RTL for digital and mixed signal IP blocks, run synthesis exploration, and support DFT/ATPG flows to create semiconductor IP for automotive, mobile, data center, HPC, and AI applications.
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STA & Synthesis Lead Engineer↗ SemidynamicsBarcelona, CT, ES 7d Lead engineer driving logic synthesis, static timing analysis (STA), and timing closure for complex digital designs from RTL to implementation, ensuring Power, Performance, and Area (PPA) targets are met.
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Staff SoC RTL Engineer Quadric Pty LtdBurlingame, CA (HQ) $170k–$170k7d Design and integrate SoC-level subsystems for a General Purpose Neural Processing Unit (GPNPU) enabling neural network inference and C++ code on a single programmable architecture for edge devices.
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