ASIC Physical Design
1,648 open positions
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VLSI Engineer II Graduate HpeSunnyvale, California, United States of America $106k–$214k9d Designs, simulates, tests, and develops VLSI components, hardware systems, and computer/server architectures for prototype and production solutions.
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Senior Engineer, GPU RTL Design - Pixel Pipe Samsung Electronics3655 N 1st St, San Jose, CA, USA $139k–$139k9d Design and develop complex RTL blocks and subsystems for Samsung's next-generation mobile GPU IPs, focusing on pixel processing and graphics pipeline stages.
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Physical Design Methodology CAD Engineer AppleSanta Clara, United States of America 9d Designing and manufacturing next-generation, high-performance, power-efficient system-on-chip (SoC) processors for Apple devices.
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Digital IC Design Intern, BS - Summer 2027 MarvellSanta Clara, CA, US $62k–$123k9d Intern role focused on digital IC design, RTL development, and verification for high-performance Ethernet PHY chips and SoC subsystems.
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Physical Design Implementation and Signoff Methodology Lead & Architect AlteraSan Jose, California, United States $232k–$232k9d Architect and own the end-to-end physical design implementation and signoff methodology (place-and-route, EMIR, timing, power) across Altera's FPGA product portfolio, integrating AI/ML techniques to improve closure speed and quality.
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GPU Engineering Manager IntelUS, California, Santa Clara $221k–$312k9d Design and develop high-quality GPU hardware platforms for high-performance computing, graphics, and visualization, leading the process from feasibility studies through tapeout and power-on.
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AI芯片供电解决方案高级技术专家 HuaweiDongguan, China 10d Lead the design of power supply solutions for AI chips, ensuring manufacturability, reliability, and optimal power efficiency to maximize compute performance.
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Senior AI STA Engineer, Sub-chip NVIDIAIsrael, Yokneam 12d Senior AI Static Timing Analysis (STA) Engineer performing advanced STA for complex chiplet and full chip levels, utilizing AI for timing optimization and data analysis in STA and PnR.
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RTL Intern EtchedSan Jose 12d Design microarchitecture and implement logic in Verilog for cutting-edge machine learning architectures.
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Next Gen CPU Power Management RTL Design Engineer↗ AMDSanta Clara, CA, US 12d Design core clocking, reset, and power management IP for next-generation AMD processors (Ryzen, Threadripper, Epyc).
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Processor Core Logic Design/Architect CadenceAUSTIN 12d Architect and design enhancements to processor core logic, partnering with the Chief Architect to identify and solve performance opportunities.
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Principal Hardware Architect – ASIC & System Integration, Cisco Silicon One (Hybrid) CiscoMilpitas, California, US $234k–$234k12d Principal Hardware Architect driving ASIC system integration, signal/power integrity, and thermal design for high-performance networking silicon.
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Director, Digital Design AnalogdevicesIndia, Bangalore, RMZ 12d Lead digital design activities and provide technical leadership for silicon development across one or more products.
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Senior AI Silicon Architect MicrosoftUnited States, California, Mountain View 12d Provide technical leadership for early specification and architecture of silicon ASICs, specifically for AI accelerators, focusing on security, debug, telemetry, RAS, error handling, firmware/software interfaces, and power management.
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Manager, Digital Design AsteralabsSan Jose $216k–$216k12d Lead front-end digital design of high-performance PCIe, CXL, UAL, and ethernet devices for rack-scale AI infrastructure.
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Graduate Digital Design Engineer Renesas-ElectronicsEdinburgh, gb 12d Designing complex ASIC systems including digital control and data-path systems for automotive, industrial, infrastructure, and IoT applications.
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Digital IC Design Engineer | BGP Texas InstrumentsDallas, TX, United States 13d Define, develop, and refine the digital portion of battery gauge mixed signal SOCs, translating system intent into micro-architecture, RTL, and production-ready hardware.
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Senior RISC-V Digital IP Design Engineer ON SemiconductorBrno, South Moravia, Czech Republic 13d Define and implement configurable RISC-V CPU IP for real embedded products, covering the full lifecycle from architectural exploration to tape-out.
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Sr Principal VLSI Engineer↗ Hewlett Packard Enterprise | HpeSunnyvale, CA, US $174k–$353k13d Designs, analyzes, develops, and evaluates VLSI components and hardware systems, determining architecture and logic design while building physical implementations of complex integrated circuits.
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Physical Design Engineer↗ Micron TechnologyTlaquepaque, JAL, MX 13d Drive semicustom physical implementation from netlist handoff through tapeout for advanced semiconductor products.
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Memory Subsytem Expert, MLA Technology
AmazonAustin, Texas, United States
$159k–$215k13d
Design, validate, and operate memory subsystems (HBM, SRAM, UCIe) for next-generation machine learning chips and servers.
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New College Grad - Engineer, ASIC Digital Design MicronMinneapolis, MN $86k–$86k13d Design and develop RTL for next-generation DRAM memory controllers and subsystems using SystemVerilog, supporting simulation, validation, and chip bring-up.
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