FE Engineering
Core
Optimizing and implementing designs for chips in hardware devices, focusing on synthesis, timing analysis, and power integrity.
Role type
Senior IC physical design engineer (chip synthesis & timing)
Builds
Physical chip designs for hardware devices
Domain
Semiconductor / Hardware Engineering
Required skills
VLSI design, RTL synthesis, Static timing analysis, Power integrity checks, Signoff verification, Engineering Change Order (ECO) implementation, CAD tool integration, Lint checks, Logic optimization, Scripting (Perl, Python), HDL knowledge, Simulation and debugging tools, GPU architecture understanding
Preferred skills
N/A
Technologies
Perl, Python, HDL, CAD tools, Simulation tools
Responsibilities
Design synthesis to convert Register Transfer Level code to digital logic gates; Perform Static timing analysis and constraint development; Conduct Power integrity checks; Execute Signoff checks for design quality; Implement Engineering Change Orders; Collaborate with CAD teams and tool vendors; Create innovative flows for new chip designs; Perform Lint checks on RTL code; Optimize logic designs for low power, low area, and high performance.
Seniority
Mid-level, hands-on IC
