FE Engineer
Core
Designing RTL microarchitecture blocks for CPU-based SoCs and optimizing power/performance.
Role type
Senior IC RTL Design Engineer (SoC)
Builds
CPU-based System-on-Chip (SoC) blocks and IP integrations
Domain
Semiconductor hardware design
Required skills
System Verilog, Verilog, CDC analysis, AMBA protocols, industry standard simulation tools, digital/analog IP integration, timing analysis, LINT tools, silicon bring-up debugging
Responsibilities
Define design microarchitecture, develop RTL design for blocks, integrate shared IP blocks, complete front-end synthesis/STA, optimize power/performance, collaborate with multi-disciplinary groups for delivery
Seniority
Mid-level, hands-on IC
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