Senior SoC / RTL Design Engineer
Core
Design and verification of IPs and compute subsystems for mobile, server, IoT, and automotive SoCs.
Role type
Senior IC RTL Design Engineer
Builds
Fully integrated and optimized SoC IPs and subsystems
Domain
Semiconductor / SoC Design
Required skills
SystemVerilog, Verilog HDL, RTL design, EDA tools, static design checks, power/clock domain crossing, synthesis, computer architecture fundamentals, scripting (Python/Perl/Unix)
Preferred skills
Arm-based designs, AMBA protocols, C/C++/assembly, Functional Safety (ISO 26262), low-power design (UPF/CFP)
Technologies
SystemVerilog, Verilog, Python, Perl, Unix shell, EDA tools
Responsibilities
Write micro-architecture specifications, develop RTL, run design checks, review test plans, debug design issues, optimize designs, plan work and report status
Seniority
Senior, hands-on IC
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