FE Engineering
Core
Design digital control logic for Power Management ICs (PMICs) using SystemVerilog, ensuring PPA targets are met for silicon tapeout.
Role type
Senior IC digital design engineer (ASIC/PMIC)
Builds
Digital control logic and PMICs for Apple products
Domain
Semiconductor hardware design (ASIC)
Required skills
SystemVerilog, RTL design, FSM implementation, Synopsys Design Compiler, Cadence Genus, PrimeTime PX, Cadence Xcelium, Simvision, Clock Domain Crossing (CDC) analysis, Reset Domain Crossing (RDC) analysis, Perl scripting, Python scripting, STA analysis, power estimation
Preferred skills
N/A
Technologies
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime PX, Cadence Xcelium, Simvision, Perl, Python
Responsibilities
Design digital control logic in SystemVerilog for PMICs; Synthesize RTL designs into gates and analyze PPA impact; Perform RTL simulation and functional verification; Conduct CDC and RDC analysis and verification; Manage design signoff duties including constraint file cleanup; Utilize scripting languages for ASIC flow tasks; Support Silicon Validation team with debugging and test plan reviews.
Seniority
Senior, hands-on IC
