FE Engineering
Core
Own full-chip and block-level timing closure for complex multi-clock, multi-voltage SoCs in deep sub-micron processes for high-end mobile applications.
Role type
Senior IC physical design engineer (timing closure)
Builds
System-on-Chip (SoC) designs for high-end mobile devices
Domain
Semiconductor hardware design, deep sub-micron ASIC
Required skills
Static Timing Analysis (STA), RTL programming (Verilog/VHDL), Python/C++ scripting, digital logic design, analog circuit effects, clock domain management, FSM design, netlist debugging
Preferred skills
N/A
Technologies
Verilog, VHDL, Python, C/C++, deep sub-micron processes
Responsibilities
Develop and enhance timing constraints for complex SoCs; create timing constraint and coverage analysis scripts; perform critical path analysis; resolve complex timing issues with cross-functional teams; own timing closure from RTL through physical implementation; develop methodology for timing verification.
Seniority
Senior, hands-on IC
