Physical Analysis Engineer
Core
Debug flow issues and perform electrical analyses (Static/Dynamic IR, EM, Noise) for ASIC physical design to ensure signoff closure for tape out.
Role type
Senior IC physical analysis engineer (ASIC)
Builds
ASIC chips and power grid networks (PDN)
Domain
Semiconductor / Hardware Design
Required skills
ASIC physical design, floor planning, clock and power distribution, electrical analysis (IR, EM, Noise), power gating, clock gating, post-silicon correlation, scripting (Perl, Tcl, Python), PDN analysis
Preferred skills
N/A
Technologies
Apache Redhawk, Voltagestorm, ETS, PT-SI, Ansys RedHawk, Cadence Voltus
Responsibilities
Debug flow related issues, perform static and dynamic power analysis, utilize problem-solving skills to debug complex EMIR violations, conduct chip-package co-analysis, create or automate complex engineering workflows, perform post-silicon correlation
Seniority
Senior, hands-on IC
