Staff SoC RTL Engineer
Core
Design and integrate SoC-level subsystems for a General Purpose Neural Processing Unit (GPNPU) enabling neural network inference and C++ code on a single programmable architecture for edge devices.
Role type
Staff SoC RTL Engineer
Builds
Next-generation SoC platform for automotive, industrial, robotics, and embedded systems
Domain
Semiconductor / Edge AI / Computer Architecture
Deliverable
production ML models
Required skills
SoC/ASIC front-end design, SystemVerilog, Verilog, computer architecture, low-power digital design, third-party IP integration, VCS, Verilog/C Co-Simulation
Preferred skills
logic synthesis, performance modeling, FPGA design, automotive safety standards (ASIL), hardware security standards
Technologies
SystemVerilog, Verilog, VCS, C, NoC, PCIe, UCIe, DDR
Responsibilities
Own SoC-level subsystem development and integration with third-party IP; Define SoC architecture based on application requirements; Optimize Power, Performance, and Area (PPA) at the SoC level; Achieve timing closure across the full product lifecycle; Package designs for customer releases and iterate based on feedback
Seniority
Staff, hands-on IC with strategic ownership
