Senior IP Design Verification Engineer
Core
Lead verification of complex flows at subsystem, IP, or block level, developing UVM-based environments and applying generative AI to drive quality and efficiency.
Role type
Senior IC IP Design Verification Engineer
Builds
Pre-silicon subsystem or IP verification for full product cycles
Domain
Semiconductor hardware verification (IP/Subsystem)
Deliverable
production ML models
Required skills
UVM, System Verilog, Python, random-stimulus generation, coverage-driven verification, generative AI application, technical leadership, cross-team coordination
Preferred skills
Experience with fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, power management, protocol bridges, CHI, AMBA, AXI protocols
Technologies
UVM, System Verilog, Python, Python-based post-processing
Responsibilities
Own or lead verification of complex flows at subsystem, IP, or block level; Develop UVM-based verification environments and run/debug simulations; Apply random-stimulus and coverage-based techniques to find bugs; Innovate to improve verification efficiency through methodologies or tools; Apply industry leading generative AI solutions to verification work; Coach and mentor others through knowledge sharing
Seniority
Senior, hands-on IC with technical leadership
