SoC Physical Design Engineer
Core
Own physical design cycle (netlist to GDS) for large-scale SoCs, including implementation and verification.
Role type
SoC Physical Design Engineer
Builds
Next-generation Apple SoCs
Domain
Semiconductor / SoC Physical Design
Required skills
Block-level PnR, floor-planning, clock/power planning, static timing closure, physical verification, electrical/power analysis (EM/IR-Drop/Xtalk/noise), place & route tools (Synopsys/Cadence), scripting (TCL/Python/Perl/Shell)
Preferred skills
Verilog
Technologies
Synopsys, Cadence, TCL, Python, Perl, Shell
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