AMS STA / Timing Engineer (m/f/d)
Core
Backend focal point for timing and constraints development to achieve sign-off quality timing constraints for Analog Mixed Signal IPs.
Role type
Senior IC Static Timing Engineer (ASIC)
Builds
Analog Mixed Signal IPs
Domain
Semiconductor / ASIC Design
Required skills
ASIC timing closure flow, Static Timing Analysis (STA) tools (Primetime), timing corners/modes, process variations, signal integrity, SDC constraints generation, Tcl scripting, Perl scripting, synthesis methodology, DFT methodology, backend design methodology
Preferred skills
Bachelor or Master's degree in Electrical Engineering
Technologies
Primetime, Tcl, Perl, SDC
Responsibilities
Develop and own full chip, IP, and block level timing constraints from synthesis to sign-off; Collaborate with RTL designers to understand design intent and clock structure; Collaborate with CAD and Physical Design teams to close and sign-off timing; Innovate timing constraints and flow to facilitate timing closure and address pessimism or fallouts in timing analysis.
Seniority
Senior, hands-on IC
