Experienced Analog Design Engineer (m/f/d)
Core
Design high-performance, high-speed Analog Mixed-Signal (AMS) circuits for SerDes PHY components including bias generators, clock distribution, and oscillators.
Role type
Senior IC Analog Design Engineer (SerDes/AMS)
Builds
Block-level AMS IP and transistor-level implementations for high-speed serial links
Domain
Semiconductor / High-Speed Analog Mixed-Signal Design
Required skills
Analog mixed-signal circuit design, high-speed serial link design, Bandgap/biasing/LDO/amplifier/comparator/ADC/DAC/Oscillator/Filters design, mismatch mitigation, linearity, stability, low-power/low-noise techniques, digitally assisted analog design, Tx/Rx equalization (CTLE/DFE/de-emphasis), CDR architectures, FinFet technology, IC development lifecycle (layout to production), SystemVerilog/Matlab/Python/VerilogAMS
Preferred skills
Timing closure concepts, high-speed serial I/O lab testing and debug, SerDes protocols (PCIe/USB/DP/MPHY), scripting and automation
Technologies
FinFet, SystemVerilog, Matlab, Python, VerilogAMS, Nanotime, Primetime
Responsibilities
Evaluate circuit topologies for specific product requirements, create block-level specifications, execute transistor-level implementation and behavioral modelling, drive mask design for layout implementation, interact with cross-functional teams (architecture, SIPI, packaging, board design, DFT, ESD), communicate progress and discuss new ideas with peers/management
Seniority
Senior, hands-on IC