Front-End Implementation (Synthesis) Engineer
Core
Optimizing netlist quality and performance for GPU front-end implementation within Apple Silicon.
Role type
Senior IC physical synthesis engineer
Builds
World-class GPUs for Apple consumer products
Domain
Semiconductor / Hardware Design
Required skills
Verilog, System Verilog, scripting languages, physical synthesis, logic optimization, PPA optimization, static timing analysis, DFT insertion, multi-clock domain design, UPF, linting tools, logic equivalence tools, critical path analysis
Preferred skills
RTL design guidance, ECO implementation, cross-site IP collaboration
Technologies
Verilog, System Verilog, UPF, linting tools, logic equivalence tools
Responsibilities
Perform PPA optimization of the netlist, deliver key netlist quality milestones for partitions, collaborate with RTL and Physical design teams, analyze critical paths to guide efficient RTL designs, implement ECOs for functionality and timing
Seniority
Senior, hands-on IC
