CAD Engineer, Silicon Learning and Static Timing Analysis
Core
Analyze silicon performance data to refine static timing analysis tools, flows, margins, and design closure methodologies for high-performance, power-efficient processors and SoCs.
Role type
Senior IC CAD Engineer (Silicon Learning & Static Timing Analysis)
Builds
Next-generation, high-performance, power-efficient processor and system-on-chip (SoC) technologies
Domain
Semiconductor / Advanced Silicon Design
Deliverable
production ML models
Required skills
Static Timing Analysis, Data Mining, Statistical Analysis, Machine Learning, Design of Experiments, C, Perl, Python, Tcl
Preferred skills
DFT, Physical Design, Failure Analysis, Silicon Debug, Semiconductor Processing, Primetime, Tempus, Tetramax, Tessent
Technologies
Primetime, Tempus, Tetramax, Tessent
Responsibilities
Design experiments with design teams, DFT, CAD, and product engineering; Analyze silicon data to establish correlation metrics for design closure; Develop and deploy design closure margins to optimize power/performance tradeoffs.
Seniority
Senior, hands-on IC
