Design Verification Engineer
Core
Design Verification Engineer ensuring bug-free first silicon for IP designs and SoC components.
Role type
Senior IC design verification engineer
Builds
First silicon for IP designs and SoC parts
Domain
Semiconductor / Hardware Design
Deliverable
production ML models
Required skills
SystemVerilog, UVM, verification environment development, test-plan creation, coverage analysis, debug, LLM integration, scripting (Python/Perl/TCL)
Preferred skills
OOP, scalable test-bench development, formal verification, emulation, power-aware verification (UPF), serial/parallel protocols (PCIe, USB, DDR)
Technologies
SystemVerilog, UVM, simulators, waveform viewers, build automation tools, LLMs
Responsibilities
Study design specifications and create test plans; Develop infrastructure in SystemVerilog/UVM to stress the design; Develop and fix failures from regressions; Use LLMs to optimize verification execution
Seniority
Senior, hands-on IC
