CPU Design Timing Engineer
Core
Responsible for timing closure of CPU projects, including developing timing flows, scripting for analysis efficiency, and collaborating with micro-architects and implementation engineers.
Role type
Senior IC CPU Design Timing Engineer
Builds
High-speed digital CPU designs
Domain
Semiconductor / Digital Logic Design
Required skills
Static timing analysis (PrimeTime/Tempus), Multi-clock/power domain analysis, Noise analysis and mitigation, Variation modeling, TCL scripting, Python or Perl, SDC command usage
Preferred skills
High-speed digital design experience, Physical design methodology (synthesis, PnR, extraction), Deep sub-micron technology knowledge, CPU microarchitecture, Clock-domain crossing, RTL modeling
Technologies
PrimeTime, Tempus, TCL, Python, Perl, SDC
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