CPU Design Timing Engineer
Core
Responsible for timing closure of CPU projects, collaborating with implementation and RTL teams to ensure timing constraints are met.
Role type
Senior IC CPU Design Timing Engineer
Builds
High-performance CPU chips
Domain
Semiconductor hardware design, CPU microarchitecture
Required skills
Static timing analysis (PrimeTime/Tempus), TCL scripting, Python/Perl, SDC command usage, multi-clock domain analysis, noise analysis, variation modeling
Preferred skills
High-speed digital design experience, physical design methodology (synthesis, PnR, extraction), deep sub-micron technology knowledge, CPU microarchitecture fundamentals, clock/reset domain crossing, RTL modeling
Technologies
PrimeTime, Tempus, TCL, Python, Perl, SDC
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