FE integration & STA IP Lead- Advanced Technologies Group
Core
Lead IP timing engineer responsible for netlist generation and timing convergence from synthesis to sign-off for first silicon IP designs.
Role type
Senior IC physical design engineer (timing)
Builds
First silicon IP designs
Domain
Semiconductor / ASIC design
Required skills
ASIC timing closure flow, STA tools (Primetime), SDC constraint generation, synthesis, DFT, backend methodologies, scripting (Tcl, Perl), clock architecture understanding
Preferred skills
Timing corners/modes analysis, process variations, signal integrity, synthesis optimization
Technologies
Primetime, Tcl, Perl, Synopsys flow
Responsibilities
Own IP-level netlist generation and timing convergence journey, drive synthesis and UPF power intent, architect timing constraints for standard and custom designs, partner with RTL and Physical Design engineers, optimize CAD flows, resolve timing challenges to eliminate pessimism
Seniority
Senior, hands-on IC
