Design Verification Engineer
Core
Design Verification Engineer ensuring bug-free first silicon for IP designs and SoC components.
Role type
Senior IC design verification engineer
Builds
First silicon for Apple IP designs and SoC parts
Domain
Semiconductor hardware design
Required skills
SystemVerilog, UVM, verification environment development, test-plan development, coverage analysis, debug, LLM integration, scripting (Python/Perl/TCL)
Preferred skills
Power-aware verification (UPF), formal verification, emulation technologies, serial/parallel protocol knowledge (PCIe, USB, DDR)
Technologies
SystemVerilog, UVM, simulators, waveform viewers, build automation tools, LLMs
Responsibilities
Study design specifications and create test plans; Develop infrastructure in SystemVerilog/UVM to stress the design; Develop and fix failures from regressions; Use LLMs to optimize verification execution and quality
Seniority
Senior, hands-on IC
