SoC Physical Design Engineer, Top Level
Core
Implement complete chip design from netlist to tapeout, focusing on top-level physical design and flow optimization.
Role type
Senior IC SoC Physical Design Engineer (Top Level)
Builds
System-on-Chip (SoC) hardware products
Domain
Semiconductor / VLSI Design
Required skills
Top-level place and route (P&R), floorplanning, clock and power distribution, timing closure, physical and electrical verification, physical design construction and analysis flows, industry standard EDA tools, large SoC design experience (>20M gates), high-frequency design (>1GHz)
Preferred skills
Top-level P&R implementation, partitioning methodologies, stringent schedule and die size optimization
Technologies
EDA tools for place and route, timing analysis, power analysis
Responsibilities
Collaborate with Front-End teams to understand chip architecture and drive physical aspects early; Drive methodologies and best practices to streamline physical design work; Act as a focal point for place and route, setting goals and managing dependencies across domains; Resolve design and flow issues related to physical design.
