SoC Physical Design Engineer, Top Level
Core
Implement complete chip design from netlist to tapeout, driving physical aspects early in the design cycle and resolving design/flow issues.
Role type
Senior IC SoC Physical Design Engineer (Top Level)
Builds
High-performance System-on-Chip (SoC) hardware products
Domain
Semiconductor / VLSI Design
Required skills
ASIC integration, floorplanning, clock and power distribution, global signal planning, I/O planning, hard IP integration, hierarchical design approach, timing and physical convergence, database management, CAD tool flows (P&R, global timing verification), Design for Yield and Manufacturability, multi Vt strategies, thermal management
Preferred skills
Experience with large SoC designs (>20M gates), sub 45nm technologies, mixed signal block integration, package interactions, multiple voltage and clock domains, ESD strategies, internal and external IP integration
Technologies
P&R flows, global timing verification flows, floorplanning tools, sub 45nm process nodes
Responsibilities
Collaborate with Front-End teams to understand chip architecture and drive physical aspects early; Establish methodologies, guidelines, and checklists to streamline physical design work; Act as a focal point for place and route, setting goals, milestones, and managing dependencies; Resolve design and flow issues related to physical design and drive execution.
Seniority
Senior, hands-on IC
