Graphics Cache Hierarchy Design Verification Engineer
Core
Pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects, and Link interface units within a high-performance GPU design.
Role type
Senior IC verification engineer (graphics cache hierarchy)
Builds
Pre-silicon verified RTL for GPU memory subsystems
Domain
Semiconductor / GPU architecture
Required skills
Verilog, System Verilog, Object Oriented Programming, Data Structures, Computer Architecture, Test Plan Authoring, Debugging, HDL Simulators, Waveform Viewers
Preferred skills
GPU/CPU architecture background, Perl, Ruby, Shell scripting, Makefiles, Caches, Address Translation Units
Responsibilities
Author test plans for block or subsystem level functionality, architect and develop complex verification software components, debug and close blocks in collaboration with design teams, work on test benches ranging from sub-blocks to subsystems
Seniority
Mid-level, hands-on IC
