SoC UPF Methodology Engineer
Core
Enhance Unified Power Format (UPF) methodologies, refine power intent specifications, and integrate AI/ML to optimize low-power chip design workflows for mobile SOCs.
Role type
Senior IC SoC UPF Methodology Engineer
Builds
Low-power ASICs for mobile products
Domain
Semiconductor / Low-power chip design
Deliverable
production ML models
Required skills
UPF implementation and verification, Python scripting, Tcl scripting, CMOS power design principles, static and dynamic verification techniques, RTL-to-GDSII design flow knowledge
Preferred skills
AI/ML application for workflow optimization, multi-voltage static verification tools (VSILP/VCLP, CLP), power ERC sign-off
Technologies
Python, Tcl, VSILP, VCLP, CLP
Responsibilities
Enhance power intent coverage via advanced static and dynamic verification techniques; Develop tailored UPF solutions for unique project requirements; Oversee UPF deployment and sign-off for frontend and place-and-route stages; Conduct power intent assessments on custom circuitry; Partner with design and verification teams to troubleshoot UPF workflow challenges; Integrate AI/ML technologies to optimize UPF processes.
Seniority
Senior, hands-on IC
