RTL Design Engineer
Core
Design and verify mixed-signal digital blocks and signal processing pipelines for Apple silicon, translating DSP algorithms into efficient RTL.
Role type
Senior IC RTL Design Engineer (mixed-signal/DSP)
Builds
High-performance mixed-signal and analog IPs integrated into high-speed digital circuits
Domain
Semiconductor / Mixed-signal silicon design
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog, DSP algorithm implementation, design verification (assertions, testbenches), lab bring-up and characterization, hardware-software co-design, scripting (Perl/Python), formal verification, low-power design
Preferred skills
Front-end tools (simulators, linters, CDC checkers), synthesis, static timing analysis, DFT, GenAI proficiency for hardware design
Technologies
Verilog, SystemVerilog, Perl, Python
Responsibilities
Develop and optimize RTL code for mixed-signal digital blocks and signal processing pipelines; Translate DSP concepts into efficient RTL implementations; Write assertions and testbenches for functional verification; Integrate complex IPs and validate performance in silicon; Support lab characterization and signal processing validation
Seniority
Senior, hands-on IC
