CPU Gate Level Synthesis Engineer
Core
Drive early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs by running RTL to gate level synthesis and optimizing timing, power, and area.
Role type
Senior IC CPU Gate Level Synthesis Engineer
Builds
High-performance, low-power CPU micro-architectural features
Domain
Semiconductor / CPU Design
Required skills
RTL synthesis, digital logic design, physical design, timing optimization, power estimation, DFT integration, constraint development, PPA analysis
Preferred skills
CPU implementation experience, scripting languages (TCL, Perl, Python) for automation, flow optimization
Technologies
RTL, gate level synthesis, scan chain, ATPG, MBIST, timing constraints
Responsibilities
Assess early RTL health for timing/gate-depth issues, estimate and validate power for new micro-architectural features, enhance synthesis flows for post-route correlation, integrate DFT components into synthesis flow, generate top-level timing constraints, debug timing/power/area issues, track PPA trends
Seniority
Mid-level, hands-on IC
