SoC Physical Design Engineer, PnR
Core
Physical implementation of design partitions from netlist to tapeout for highly complex SoCs.
Role type
SoC Physical Design Engineer (PnR)
Builds
SoC chips
Domain
Semiconductor / VLSI
Required skills
netlist to GDS2 implementation, timing signoff (STA), physical verification (DRC/LVS), power grid design, EMIR analysis, floor-planning, place and route (PnR), basic chip architecture knowledge
Preferred skills
Verilog, VHDL, Python, Perl, TCL, SPICE, computer architecture, VLSI design
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