SoC Physical Design Engineer, PnR
Core
Physical implementation of design partitions from netlist to tapeout for highly complex SoCs.
Role type
Senior IC SoC Physical Design Engineer (PnR)
Builds
SoC chips for Apple hardware products
Domain
Semiconductor / SoC Physical Design
Required skills
partition-level P&R implementation, floorplanning, clock and power distribution, timing closure, physical and electrical verification, SoC flow methodology, industry standard EDA tools, multi-voltage and clock domain handling, mixed signal block integration
Preferred skills
large SoC design experience (>20M gates), high-frequency design (>1GHz), Design for Yield and Manufacturability, multi-vt strategies, global timing verification, stringent schedule and die size adherence
Technologies
EDA tools for floorplanning, P&R flows, global timing verification, physical design verification flows
Responsibilities
Collaborate with logic design teams on partition architecture and early physical aspects; Complete netlist to GDS2 implementation meeting schedule and design goals; Perform timing, physical, and electrical verification to drive signoff closure; Resolve and improve physical design and flow issues; Optimize PnR partitions for Power/Performance/Area (PPA)
Seniority
Senior, hands-on IC
