SoC Physical Design Engineer, STA/Timing
Core
Physical implementation of design partitions from netlist to tapeout for highly complex SoCs using state-of-the-art process technology.
Role type
Senior IC SoC Physical Design Engineer (STA/Timing)
Builds
Next-generation Apple hardware products
Domain
Semiconductor / SoC Physical Design
Required skills
STA, timing closure, Perl scripting, TCL scripting, ECO implementation, timing path analysis, circuit modeling (SPICE), worst-case corner selection, noise/crosstalk/OCV analysis
Preferred skills
Large high-performance SoC design experience in sub-micron technologies, deep STA expertise, timing infrastructure implementation
Responsibilities
Debug constraints and facilitate logic changes to improve timing, create and maintain analysis scripts and methodologies, perform deep analysis of timing paths, implement timing infrastructure, create documentation and guidelines
Seniority
Senior, hands-on IC
