SoC Physical Design Verification Engineer (M, F, D)
Core
Physical verification of high-performance, power-efficient system-on-chip (SoC) processors to ensure seamless device performance.
Role type
SoC Physical Design Verification Engineer
Builds
Next-generation Apple processors and SoCs
Domain
Semiconductor / SoC Physical Design
Required skills
DRC, LVS, ERC, high voltage check, PNR tools, physical verification methodologies, TCL scripting, foundry collaboration, hierarchical design, GDS assembly, padring, bump, RDL design
Preferred skills
Analog/Digital Layout design, Mentor Calibre, floor-plan collaboration
Responsibilities
Work with physical design team to understand chip architecture and drive physical verification aspects early in design cycle; Work on full chip DRC and LVS (including understanding of the PNR tools, ERC, high voltage check); Work with physical design team, drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and supervise progress while offering physical verification support; Support partition owners with Physical Verification activities, set goals, plan short and long-term work; Resolve design and flow issues related to physical design, identify potential solutions and drive execution; Collaborate with the package and floor-plan teams.
