Mixed-Signal Verification Engineer
Core
Verification of RF and mixed-signal blocks and their interfaces within wireless System-on-Chip (SoC) designs to ensure silicon-correct functionality.
Role type
Mixed-Signal Design Verification Engineer
Builds
Wireless SoC silicon
Domain
Wireless silicon / RF / Mixed-Signal
Required skills
Mixed-Signal verification, System Verilog, UVM methodology, HDL (Verilog), Analog/RF block understanding, Testbench development, Monitor/Checker creation, Debugging, Coverage analysis, Scripting automation
Preferred skills
Python, Matlab, Virtuoso Composer, ADE, HED, Real-numbered analog behavioral modeling, Wireless experience
Technologies
System Verilog, UVM, Python, Matlab, Virtuoso Composer, ADE, HED
Responsibilities
Review specifications and extract features; Develop top/block level Mixed Signal and Digital testbenches; Build and reuse monitors and checkers; Debug failures and manage bug tracking; Write automation scripts; Improve verification methodologies
Seniority
Mid-level, hands-on IC