SoC Physical Design Verification Engineer
Core
Perform physical verification checks (LVS, DRC, DFM, DFT, lithography) at chip and block levels to ensure signoff closure for tapeout of high-performance SoCs.
Role type
Senior IC physical design verification engineer
Builds
Next-generation, high-performance, power-efficient processor system-on-chip (SoC)
Domain
Semiconductor / ASIC physical design
Required skills
Physical verification flows (DRC/LVS/ANT/HVDRC), ESD and macro placement guidelines, digital/analog mixed-signal back-end verification, scripting (Perl/Python/Tcl), industry standard tools (Mentor Calibre, Synopsys ICV), tapeout signoff experience
Preferred skills
Layout design, full-chip integration methodology
Technologies
Mentor Calibre, Synopsys ICV, Perl, Python, TCL
Responsibilities
Perform physical verification checks at chip and block level, collaborate with CAD/Technology teams for flow bring up and validation, lead schedules and support cross-functional engineering efforts, work on padring, bump, RDL design, and coordinate with package and floorplan teams
Seniority
Senior, hands-on IC
