SoC Physical Design Verification Engineer
Core
Perform physical verification checks (LVS, DRC, DFM, DFT, lithography) at chip and block levels to ensure signoff closure for tapeout of high-performance, power-efficient SoCs.
Role type
Senior IC physical design verification engineer
Builds
Next-generation system-on-chip (SoC) processors for Apple devices
Domain
Semiconductor / SoC Physical Design
Required skills
LVS, DRC, DFM, DFT, lithography verification, RTL to GDS flow knowledge, scripting for flow debugging, industry standard verification tools (Mentor Calibre, Synopsys ICV)
Preferred skills
Layout design, padring, bump, RDL design, package and floorplan integration
Technologies
Mentor Calibre, Synopsys ICV
Responsibilities
Perform physical verification checks (LVS, DRC, DFM, DFT, lithography), collaborate with CAD/Technology teams for flow bring up and validation, lead schedules and support cross-functional engineering efforts, work on padring, bump, RDL design, and coordinate with package and floorplan teams
Seniority
Entry-level (0 years experience required)
