FE RTL Infrastructure - CAD Engineer
Core
Design and maintain infrastructure, version control, and configuration management systems for RTL design and verification teams at Apple.
Role type
Senior IC infrastructure engineer (RTL/CAD)
Builds
Reliable infrastructure and work environments for RTL design and verification flows
Domain
Semiconductor / Hardware Design / EDA
Deliverable
infrastructure
Required skills
Python, Perl, Verilog, SystemVerilog, Perforce administration, centralized configuration management, generative AI integration
Preferred skills
Front-End EDA tools (Clock Domain Crossing, Reset Domain Crossing, Lint), RTL build/construction flows, large-scale software system development
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