CPU Design Timing Engineer
Core
Responsible for timing closure of CPU block-level implementation projects.
Role type
Senior IC CPU Design Timing Engineer
Builds
High-performance CPU blocks
Domain
Semiconductor / CPU Design
Required skills
Static timing analysis, multi-clock domain handling, power domain management, scripting (TCL/Perl/Python), cross-talk analysis, noise analysis, OCV, uncertainty modeling, derate methodology
Preferred skills
CPU microarchitecture knowledge, low-power implementation techniques, physical design flows (synthesis, place & route), physical design verification (LEC, DVS), device physics
Technologies
Primetime, Tempus, TCL, Perl, Python
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