Analog Design Engineer - SERDES
Core
Design high-performance, high-speed AMS circuits for SerDes PHY components including Rx, CDR, Tx, bias generators, and clock distribution to meet PPA targets.
Role type
Senior IC Analog Designer (SerDes PHY)
Builds
Block-level specifications and transistor-level implementations for high-speed serial link IP.
Domain
Consumer Electronics / High-Speed Analog Mixed-Signal
Required skills
Analog mixed-signal circuit design, high-speed serial link experience, Bandgap/biasing/LDO/amplifier/comparator/ADC/DAC/Oscillator/Filter design, mismatch mitigation, linearity, stability, low-power/low-noise techniques, digitally assisted analog design, high-speed digital circuits, Tx/Rx equalization (CTLE, DFE, de-emphasis), CDR architectures, lab equipment operation, AMS IC development lifecycle, FinFet technology, layout supervision, bench evaluation, correlation, characterization.
Preferred skills
Timing closure concepts, high-speed serial I/O debug and data analysis, SerDes protocols (PCIe, USB, DP, MPHY), scripting and automation.
Technologies
SystemVerilog, Matlab, Python, VerilogAMS, Nanotime, Primetime
Responsibilities
Evaluate circuit topologies for specific product requirements, create block-level specifications, execute transistor-level implementation and behavioral modelling, drive mask design for layout implementation, interact with cross-functional teams (architecture, SIPI, packaging, board design, DFT, ESD), communicate progress and discuss new ideas with peers/management.
Seniority
Senior, hands-on IC