Mixed Signal RTL Design Engineer
Core
Specify, design, and verify RTL blocks for advanced mixed-signal circuits, collaborating with system architects and circuit designers to ensure bug-free silicon and timing closure.
Role type
Senior IC mixed-signal RTL design engineer
Builds
RTL blocks for mixed-signal circuits
Domain
Semiconductor / Mixed-signal IC design
Required skills
RTL coding, Verilog, System Verilog, Mixed-signal concepts, Algorithm development, Physical design collaboration, Front-end tools (simulators, linters, CDC/RDC checkers), Synthesis, Static timing, DFT, Scripting (Perl, Python)
Preferred skills
System-Verilog assertions and checkers, Design verification techniques
Technologies
Verilog, System Verilog, Perl, Python, LINT, CDC, RDC
Responsibilities
Write detailed design specifications, collaborate with system architects and circuit designers, use formal tools to guarantee RTL quality, support design verification for bug-free silicon, work with the PD team for timing closure, support silicon bring up
Seniority
Senior, hands-on IC