SoC Physical Design Engineer, PnR
Core
Lead physical design implementation from RTL to GDS for high-performance, low-power SoCs, focusing on timing closure, area, and power optimization.
Role type
Senior IC SoC Physical Design Engineer (PnR)
Builds
High-performance System-on-Chip (SoC) physical architectures
Domain
Semiconductor / VLSI Physical Design
Required skills
PnR, bump/RDL, STA, physical verification, EMIR, sign-off, floorplanning, clock & power distribution, timing closure, physical & electrical verification, PD construction & analysis flows, tapeout execution, large SoC design experience (>20M gates), industry standard tools
Preferred skills
partition level P&R implementation, methodology development, deep submicron technology expertise, large SoC design execution (>20M gates, >1GHz), schedule & die size optimization
Technologies
industry standard physical design tools
