GPU Physical Design Engineer, STA/Timing
Core
Lead Static Timing Analysis (STA) and timing closure for high-performance, power-efficient GPU processors in Apple products.
Role type
Senior IC physical design engineer (STA/Timing)
Builds
Next-generation GPU silicon for Apple devices
Domain
Semiconductor / GPU Physical Design
Required skills
Static Timing Analysis (STA), timing closure, cross-talk analysis, OCV, noise analysis, TCL scripting, Python scripting, Perl scripting, shell scripting, EDA tool APIs, ECO flows, tapeout signoff checks, post-silicon debug, PPA optimization
Preferred skills
Master's degree in CS/CE, driving timing closure track record, constraint management for multiple timing modes, post-silicon timing correlation, new process technology enablement, frequency target setting for future generations
Technologies
TCL, Python, Perl, Shell, EDA tools
Responsibilities
Lead concurrent STA activities and identify roadblocks for timing closure; Collaborate with RTL, Architecture, Synthesis, and Physical Design teams on timing constraints; Set up DFT modes and ensure test features are properly timed; Assemble top-level design for STA and review logs/reports; Run ECO flows and drive tapeout activities with full signoff checks; Work with CAD vendors to improve analysis flows; Support post-silicon debug and timing correlation.
Seniority
Senior, hands-on IC
