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IC Packaging Integration Engineer

San Francisco Bay Area, United States of America💼 Full-time🗓 2026-07-24 → 2026-09-28

Core

Lead package integration and architecture efforts to bring innovative packaging solutions from concept to mass production for advanced semiconductor products.

Role type

IC Packaging Integration Engineer (Lead)

Builds

Advanced package solutions, modules, and technology developments for high-volume manufacturing

Domain

Semiconductor industry, advanced packaging

Required skills

Semiconductor packaging design, process & technology development, Si floor plan, package layout and architecture, enabling process technologies, thermal management, mechanical design, signal integrity (SI), power integrity (PI), material selection, component & system level reliability, testing, failure analysis (FA), high density interconnects, SiP packaging, physics fundamentals, design for manufacturing, BOM management, cost optimization

Preferred skills

MS/PhD in relevant field, experience with Cadence APD/Allegro tools, background in advanced SiP packaging

Technologies

Cadence APD, Allegro

Responsibilities

Lead package co-design with Silicon, Packaging, and Systems teams; drive package technology development; co-work with assembly partners on NPI and qualification; create package design documentation and technical risk assessments

Seniority

Senior, hands-on IC

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