Graphics Cache Hierarchy Design Verification Engineer
Core
Pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects, and Link interface units for high-performance, power-efficient processors.
Role type
Senior IC verification engineer (graphics cache hierarchy)
Builds
Next-generation, high-performance, power-efficient processor, system-on-chip (SoC)
Domain
Semiconductor / Computer Architecture / Graphics
Required skills
CPU or GPU architecture knowledge, verification methodology, SystemVerilog, HDL simulators, waveform viewers, unit or cluster level test environment development, bring up and debug of complex designs
Preferred skills
Cache verification, memory subsystem testing, Graphics Pipeline understanding, UVM, coverage space definition and closure, Perl/Ruby/Shell scripting, Makefiles
Technologies
SystemVerilog, VHDL, Verilog, UVM, HDL simulators, waveform viewers
Responsibilities
Develop verification plans in coordination with design leads and architects; Build and maintain portable verification test bench components and environments; Generate directed and constrained random tests; Run simulations and debug design and environment issues; Create functional coverage points, analyze coverage, and improve test environment to target coverage holes; Create automated verification flows for block verification
Seniority
Mid-level, hands-on IC
