SoC Physical Design Engineer, PnR
Core
Physical implementation of design partitions from netlist to tapeout for highly complex System-on-Chip (SoC) utilizing innovative process technology.
Role type
Senior IC SoC Physical Design Engineer (PnR)
Builds
SoC chips for Apple hardware products
Domain
Semiconductor / VLSI Physical Design
Required skills
partition-level P&R implementation, floorplanning, clock and power distribution, timing closure, physical and electrical verification, physical design flow methodology, optimization for Power/Performance/Area
Preferred skills
large SoC design experience (>20M gates), high-frequency design (>1GHz), Design for Yield and Manufacturability, multi-vt strategies, mixed signal block integration, global timing verification
Technologies
industry standard P&R and verification tools
Responsibilities
Collaborate with logic design teams on partition architecture, complete netlist-to-GDS2 implementation, perform signoff closure, resolve physical design flow issues, optimize partitions for PPA
Seniority
Senior, hands-on IC