SerDes Design and Validation Engineer
Core
Lead system validation, bring-up, and debug of mixed-signal SerDes IP for high-performance analog and mixed-signal circuits.
Role type
Senior IC analog/mixed-signal validation engineer
Builds
High-performance SerDes PHYs for Apple products
Domain
Semiconductor, high-speed serial links
Required skills
SerDes system bring-up and validation, analog mixed-signal circuit design, DFT development, mixed-signal verification, lab and production testing, data analysis, scripting and automation, high-speed serial link protocols (PCIe, USB, DP, MPHY), Tx/Rx equalization techniques, CDR architectures
Preferred skills
Experience with Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters, digitally assisted analog design, layout supervision, bench evaluation, correlation, characterization, firmware assisted mixed signal IP development, AI/ML concepts for silicon performance
Technologies
ATE, PCIe, USB, DP, MPHY, CTLE, DFE, de-emphasis, LMS based adaptive loops
Responsibilities
Own SerDes system bring-up, validation, and debug in system environment; work with design teams to define DFT needs; perform mixed-signal verification tasks; drive lab and production testing, debug, and data analysis
Seniority
Senior, hands-on IC