CAD Engineer – PDV
Core
Architect, develop, and maintain physical design verification (PDV) flows for high-performance, power-efficient silicon chips from full custom analog to multi-die SoC.
Role type
Senior IC physical design verification engineer
Builds
Physical verification flows, runsets, and custom rule decks for chip manufacturing
Domain
Semiconductor / Silicon chip design
Required skills
Calibre/ICV runset coding, DRC/LVS/ERC/MFILL rule development, PnR flow expertise, Perl/Python/Tcl/Shell/C++ scripting, DFM/Dummy Metal Fill knowledge, SoC PDV debug
Preferred skills
PERC rule coding, Parasitic extraction, Virtuoso SKILL coding, PnR tools hands-on experience
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