CAD Engineer – PDV
Core
Architect, develop, and maintain physical design verification (PDV) flows for high-performance, power-efficient silicon chips.
Role type
Senior IC physical design verification engineer
Builds
Physical verification flows and rule decks for custom analog, digital, and mixed-signal SoCs
Domain
Semiconductor / Silicon chip design
Required skills
Calibre/ICV runset coding, DRC/LVS/ERC/MFILL rule development, PnR flow expertise, Perl/Python/Tcl/Shell/C++ scripting, DFM/Dummy Metal Fill knowledge
Preferred skills
PERC rule coding, PnR tools usage, Parasitic extraction knowledge, Virtuoso SKILL coding
Technologies
Calibre, ICV, PERC, Perl, Python, Tcl, Shell, Makefile, C++, Virtuoso
Responsibilities
Develop and improve physical verification flow and methodology; Coordinate validation of flows and custom checks; Code custom PDV rule decks (ERC, Programmable ERC); Collaborate with tool vendors and foundries for PDK enhancements
Seniority
Senior, hands-on IC
