DRAM Design Validation Engineer
Core
Ensuring successful integration of DRAM memories with SoC devices and validating memory controller and PHY requirements for Apple's processors.
Role type
DRAM Design Validation Engineer
Builds
Next-generation, high-performance, power-efficient processors and Systems-on-Chip (SoC)
Domain
Semiconductor / Memory Interface
Required skills
DRAM simulation, memory interface verification, DDR-PHY design, memory controller design, failure analysis, DRAM reliability principles, LPDDRx I/O characterization, advanced packaging knowledge (PoP, TSV), Python programming
Preferred skills
DRAM cell architecture knowledge, low-power DRAM periphery design, hardware/software debugging, computer architecture background
Technologies
Python, LPDDRx, PoP, TSV
Responsibilities
Collaborate with design and verification engineers to define memory controller and PHY requirements; Partner with Architecture, MCU, and vendor teams to validate memory features; Ensure DRAM simulations meet performance, power, and reliability targets; Define silicon and package-level testing needs; Debug RMA materials and drive root cause analysis; Work with vendors to improve memory performance and efficiency; Drive roadmaps and technical specifications for next-generation nodes.