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Emulation Verification Engineer

San Francisco Bay Area, United States of America💼 Full-time🗓 2026-08-13 → 2026-09-28

Core

Verification of large Wireless SoCs using emulation platforms, including porting designs and executing test plans.

Role type

Emulation Verification Engineer

Builds

Verified Wireless SoC designs on Palladium emulation platform

Domain

Semiconductor / Chip Design / Wireless SoC

Required skills

System Verilog, Verilog, UVM, Palladium platform, mixed signal modeling, test plan execution, cross-functional collaboration, C/C++ DPI, scripting (Perl/Python/TCL), UPF, assertions

Preferred skills

Emulation bring-up and debugging, RTL to Emulation tool flow, Standard Emulator (Veloce, Zebu) or FPGA (Xilinx, Altera) flow, Design Verification, Silicon Validation, Synthesize-able code, UVM Acceleration, Low Power methodologies

Technologies

Palladium, Veloce, Zebu, Xilinx, Altera, Verilog, System Verilog, UVM, C++, Perl, Python, TCL, UPF

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