Emulation Verification Engineer
Core
Verification engineer responsible for bringing up large Wireless SoCs and mixed-signal components on emulation platforms, executing test plans, and developing verification code.
Role type
Senior IC emulation verification engineer
Builds
Verified large Wireless SoCs and mixed-signal components on Palladium emulation platform
Domain
Semiconductor hardware design and verification
Required skills
System Verilog, Verilog, UVM, test bench creation (block/system level), regression management, triaging, Palladium platform, mixed-signal modeling, cross-functional collaboration
Preferred skills
Emulation bring-up and debugging, RTL-to-emulation tool flow, FPGA flow (Xilinx/Altera), silicon validation, synthesizable SystemVerilog with assertions, C/C++ DPI, scripting (Perl/Python/TCL), low power methodologies (UPF), UVM acceleration
Technologies
Palladium, Verilog, System Verilog, UVM, C/C++, Perl, Python, TCL, UPF, Xilinx, Altera, Zebu, Veloce
Responsibilities
Port designs onto the Palladium platform, execute detailed emulation test plans, develop and utilize monitors and checkers, collaborate with Design, Architecture, Power, Silicon Validation, Performance, and SW teams
Seniority
Senior, hands-on IC
