GPU Internships - RTL Design, RTL Power Optimisation & Physical Design
Core
Interns assist in delivering high-quality IP for Apple Silicon SoCs, focusing on RTL design, power optimization, and physical design to meet performance, timing, area, and power goals.
Role type
Academic year intern (RTL Design / RTL Power Optimisation / Physical Design)
Builds
GPU IPs for Apple Silicon SoCs
Domain
Semiconductor hardware design (ASIC/GPU)
Required skills
C/C++ coding, SystemVerilog/Verilog/VHDL, scripting (Perl/Python/Ruby), chip architecture knowledge
Preferred skills
STA, Synthesis, floorplanning, placement, routing, automation scripting
Responsibilities
Collaborate with design, verification, and physical design teams; analyze and optimize power takedown strategies; work through physical design aspects from floorplanning to routing; write scripts to automate flows and improve metrics
Seniority
Intern
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