ASIC Design Engineer — Pixel IP
Core
Design high-performance, low-power pixel processing engines and digital signal processing pipelines for capturing, improving, compressing, and displaying digital still images and video.
Role type
Front-end ASIC Design Engineer (Pixel IP)
Builds
Pixel IP for Apple SoCs
Domain
Consumer electronics / Digital imaging
Required skills
RTL design (Verilog/System Verilog), Micro-architectural specification, Cross-functional collaboration, Synthesis, Timing analysis, Power analysis, Area optimization, Debugging, Formal verification
Preferred skills
SoC front-end design, Media/video/pixel/display domain experience, Low-power design techniques (clock/power-gating), On-chip bus protocols (AMBA/AXI/AHB/APB), Front-end implementation tasks (linting, CDC/RDC, logic equivalence), ASIC/FPGA methodology, Scripting (Python/Perl/TCL)
Technologies
Verilog, System Verilog, Python, Perl, TCL, AMBA, AXI, AHB, APB
Responsibilities
Design digital hardware using RTL or high-level synthesis with embedded assertions and cover points. Write detailed micro-architectural specifications. Collaborate with cross-functional teams to maximize performance while minimizing power and area. Synthesize designs and optimize for power, timing, and area. Work with verification teams to debug and verify functionality and performance.
Seniority
Mid-level, hands-on IC
